1. Field of the Invention
This invention relates generally to the field of wireless equipment design and, more particularly, to radio frequency (RF) modulator and demodulator design.
2. Description of the Related Art
The wireless world has become increasingly digitally oriented, leading Radio Frequency (RF) based design work to feature prominently in the scope of today's digital communications design. One effect of this development has been the prominence achieved by the development of modulators and demodulators, which provide a necessary RF interface for systems such as cordless phones, wireless networks, and wireless peripheral devices for computers, such as cordless mice, keyboards, etc. Considerations during design of such devices often include achieving low cost manufacturing, and assuring plug-and-play capabilities, very low power (for example, operating for a year or more on standard batteries), and high data rates for duty-cycle power savings.
There are many digital encoding standards that allow for the transmission of vast amounts of data over wireless RF interfaces in shorter periods of time. One well-known digital encoding technique based on frequency modulation (FM) is frequency shift keying (FSK), which in its simplest form provides two discrete RF frequencies that can be used as carriers to transmit two data states, which may correspond to the commonly used digital binary states of “1” and “0”, respectively. FSK modulators are many times implemented through the use of an I and Q (IQ) network performing “quadrature modulation”, where two out of phase (by 90°) carrier frequencies are modulated by the two separate digital binary states, respectively, as described above. In general, an IQ network produces two equal amplitude and quadrature phased output signals when provided with RF and Local Oscillator (LO) input signals.
Another widely used functional building block found in communications is the image reject mixer. A basic mixer is used to mix two frequencies and produce an output that consists of both the sum and difference frequencies. An image reject mixer performs the additional task of rejecting the frequency components that are produced as a result of the mixing process when one input to the mixer is an image of the desired signal. The IQ image reject up-mixer architecture incorporates the image reject mixer functionality into an IQ network operating as a quadrature modulation circuit. Commonly in such architecture, the IQ baseband channels are driven from a Digital to Analog Converter (DAC) generating the FSK modulating waveforms. Implementations of these IQ DACs are often complex due to a large number of bits required to reach adequate Signal to Noise ratios (SNRs). In addition to the complexity of the DACs, area consuming look-up tables are often used to drive these DACs. The tables typically provide the information used by the DACs to generate the modulated waveform.
Generally, most current implementations of IQ up-mixer architectures employ a vast array of standard DACs. Standard DAC implementations with low quantization noise typically require a substantial number of bits and are therefore complex, consume much more current, rely far more heavily on internal component matching, and generally consume lots more area and development time. As mentioned above, these implementations also require the use of look-up tables, which can be sizeable.
Alternative FSK modulators (direct modulators, in general) typically use a filtered digital bitstream signal to directly drive the associated Voltage Controlled Oscillator (VCO), hence omitting DACs altogether. A typical disadvantage of this approach is related to modulation accuracy, since VCOs typically have substantial tolerance on their control port. Direct VCO modulation also interferes with the PLL control loop, which places unwanted constraints on the digital bitstream, often requiring coding, for example Manchester coding. Alternatively, dual port systems are sometimes used, which in part solves the bitstream constraint issues, albeit at the expense of added complexity (added design time, current and area consumption.)
A standard direct modulation transmitter implemented in accordance with prior art is shown in FIG. 1. Data is input into a signal shaper 110, which is used to modulate a voltage controlled oscillator 120, which is part of a phase-locked loop (PLL) 106 that is connected to a power amplifier 104. Power amplifier 104 is used to transmit the modulated signal via a loop antenna 102. Signal shaper 110 may functionally be a filter, typically a low-pass filter (LPF) or a gaussian shape filter, operating to slow the edges of a Data input square wave signal in order to bring it within the operational constraints of VCO 120. PLL 106 may also include a crystal 126 providing a reference frequency to a phase frequency detector 122, which connects to an LPF 124 that is coupled to VCO 120 through summation node 128. Summation node 128 also couples the output of signal shaper 110 to VCO 120. The modulation accuracy of the transmitter shown in FIG. 1 is sensitive to the gain of VCO 120 (Kc), which may result in substantial bandwidth tolerance. Also, the bandwidth of the PLL 106 loop is constrained by the spectral content of the Data input. In other words, transfer of unlimited 1's or 0's is difficult to obtain, requiring data coding (for example Manchester coding, as mentioned above), in effect constraining the data throughput. In many aspects this design is very sensitive and highly constrained.
Therefore, there exists a need for a system and method for designing an accurate FSK modulator, which features very high accuracy in the baseband waveform, consumes low power, and can be implemented on a small die size with low complexity requiring a substantially short design time.